1. Field
This disclosure relates generally to semiconductor device packaging, and more specifically, to using conductive vias to bypass device interconnects by directly electrically coupling with molded bond wires.
2. Related Art
Package-on-package semiconductor device package connections have been adopted for three-dimensional integration of logic and memory devices within consumer devices, such as mobile handsets and portable multimedia devices. Stacking of semiconductor device packages that package-on-package techniques permit allows for increased amounts of logic and memory in a smaller space.
Existing methods of forming a package-on-package stack may not satisfy next generation applications that may require reduced memory interface pitches, higher memory interface pin-outs, reduced package thickness, tight warpage control, and higher levels of integration within the base package. Alternative methods to package-on-package techniques have included using through mold vias and through silicon vias to increase numbers of connections in devices. But these alternatives still do not resolve issues involved with wire-bond device package such as long travel distance for routing (e.g., die to substrate, substrate to solder ball, solder ball to substrate, substrate to die), which results in, for example, increased resistance and lower speed, and higher cost for the substrate design and manufacturing (e.g., bigger size, increased material usage).
It is therefore desirable to have a mechanism by which packages incorporating devices having wire bond connections can be included in three-dimensional stacking configurations while providing capacity for decreased size, decreased cost, faster signal propagation, and the like.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The figures are not necessarily drawn to scale.